1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) which has a voltage-stress applying circuit.
2. Description of the Related Art
Generally, semiconductor devices are subjected to screening before they are delivered from the factory to customers, so that only those found reliable may be supplied to the customers. In the screening, the devices are tested for latent defects which they may have, without being made defective or having their characteristics deteriorated. More specifically, a relatively high voltage is applied on each device for a short time. This voltage applied to is higher than the voltage to the device during normal use thereof. Hence, the device receives, within the short time, a stress which is greater than the stress it may receive during its early failure period. It is then determined whether or not the device can withstand the stress. If the device fails to withstand the stress, it will not be delivered from the factory. Thus, only the devices found to have withstood the stress are considered reliable and subsequently supplied to the customers.
In an early developed DRAM, an external clock-refresh signal is supplied from the refresh terminal to the refresh counter in order to effect refreshing during the ordinary operation of the DRAM. PCT International Publication Number WO 82/00917, US80/01149 (international publication date: Mar. 18, 1982), "Tape Burn-in Circuit" discloses a refreshing technique applicable to this type of a DRAM. In this technique, a burn-in signal is input to the DRAM through the wires embedded in an external tape, and a clock refresh signal is simultaneously supplied via the refresh terminal to the refresh counter. As a result, the row circuit and the column circuit are activated, and the refresh counter is actuated to output a signal to both the row decoder circuit and the column decoder circuit. Four terminals are required to perform the burn-in operation on the DRAM. They are: a power-supply terminal, a ground terminal, a burn-in mode terminal, and a refresh terminal.
The more storage capacity a DRAM has, the more terminals it has. To reduce the number of terminals, the refresh terminal, which is used to input an external clock refresh signal, is dispensed with. In this case, no refresh signal is supplied to the DRAM. Rather, the DRAM is set into a CBR refresh mode to be refreshed during its ordinary operation. While the DRAM remains in the CBR refresh mode, a CAS signal and a RAS signal are sequentially input to the DRAM through the CAS terminal and the RAS terminal, respectively, whereby a clock signal internal of the DRAM is supplied to the the refresh counter, the output of which is used as a refresh address.
Hitherto, screening is conducted on a packaged CBR-refresh mode DRAM in the following method. First, external address signals are sequentially supplied to the respective address signal terminals of the DRAM, thereby accessing the word lines of the DRAM one after another. To perform this method, the DRAM needs to have a large number of input pads, and a screening apparatus, generally known as a "prober," must be used which has an address signal generator for generating many address signals to supply to the input pads of the DRAM.
The screening method may be conducted on DRAM chips formed in a semiconductor wafer. In this case, the terminals of the prober are set into contact with the address signal pads of one DRAM chip, and address signals are sequentially supplied through the proper terminals to the respective input pads, thereby to sequentially access the word lines of the DRAM chip. To enhance the efficiency of the screening, it is desirable that the prober have many terminals so that it may supply address signals to the address signal pads of several DRAM chips at a time. (Most desirably, the prober should have as many terminals as all address signal pads on the wafer.) As a matter of fact, however, it is difficult to manufacture a prober which has a probe card with so many a terminal. Another problem is that the prober needs to incorporate an address signal generator.
To solve these problems, a screening method has been developed, which is disclosed in U.S. patent application No. 07/695,014 (filed based on Japanese Patent Application No. 2-119949). In this method, a single screening-test pad is formed on a CBR-refresh mode DRAM, and a CAS signal and a RAS signal are sequentially input to the DRAM while externally supplying a screening-test mode signal to the screening-test pad, thereby to activate the refresh counter, the row circuit and the column circuit, and the output of the refresh counter is simultaneously supplied to the row address buffer and the column address buffer.
With this method it is unnecessary to sequentially supply external address signals to the DRAM to conduct a screening test on the DRAM. Thus, the DRAM needs only five terminals, i.e., a power-supply terminal, a ground terminal, a screen-test mode terminal, a CAS terminal, and a RAS terminal. However, it is demanded that the number of input pads which a DRAM chip must have to undergo screening be reduced as much as possible in order to further enhance the screening efficiency.